1. Field of the Invention
The present invention relates generally to a memory system. More particularly, the present invention relates to a memory module providing improved signal integrity for signals transmitted via a data bus and a command/address bus. The present invention also relates to a memory system including the foregoing memory module.
A claim of priority is made to Korean Patent Application No. 2004-15592 filed on Mar. 8, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
Semiconductor memory, for example dynamic random access memory (DRAM), is widely used in computer systems such as a personal computers and servers. To improve the performance and capacity of a semiconductor memory, a plurality of semiconductor memories is typically mounted on a memory module and installed in a computer system. A conventional memory module is disclosed, for example, in published U.S. Patent Application No. 2003/0149855.
FIG. 1 illustrates a conventional memory system. Referring to FIG. 1, a conventional memory system 100 includes a memory controller 110, a memory module 120, and termination resistors RT11 and RT12, collectively mounted on a motherboard.
Memory controller 110 transmits a command/address signal to semiconductor memories DRAM1 through DRAMn included in memory module 120 through a command/address bus CABUS. The command/address signal controls the data being written to (i.e., “input”) or read from (i.e., “output”) semiconductor memories DRAM1 through DRAMn via a data bus DQBUS.
Memory module 120 includes semiconductor memories DRAM1 through DRAMn and a command/address buffer 124. Semiconductor memories DRAM1 through DRAMn are connected to data bus DQBUS and command/address bus CABUS, which are system busses connecting memory controller 110. These connections are typically made using a stub, which preferably uses conventional stub series terminated transceiver logic (SSTL).
Command/address buffer 124 buffers the command/address signal transferred through command/address bus CABUS to provide a buffered command/address signal to semiconductor memories DRAM1 through DRAMn.
First semiconductor memory DRAM1 comprises a data output buffer 121, a data input buffer 122 and a command/address input buffer 123. Data output buffer 121 buffers internal output data DOUT and transmits buffered internal output data to data bus DQBUS. Data output buffer 121 is also called a data output driver. Data input buffer 122 and command/address input buffer 123 implement pseudo-differential operators. Data input buffer 122 amplifies a voltage difference between input data transmitted through data bus DQBUS and a reference voltage VREF to generate internal input data DIN which is written to memory cells (not shown) of first semiconductor memory DRAM1. The level of reference voltage VREF is preferably half of the power supply voltage level.
Command/address input buffer 123 amplifies a voltage difference between the command/address signal transferred through command/address buffer 124 and the reference voltage VREF to generate an internal command/address signal CAI used for controlling a write or read operation of first semiconductor memory DRAM1.
Semiconductor memories DRAM2 through DRAMn are identical to semiconductor memory DRAM1 and hence descriptions of the configuration and behavior of semiconductor memory DRAM1 given herein apply to semiconductor memories DRAM2 through DRAMn as well.
Termination resistors RT11 and RT12 are constructed in a parallel termination configuration and are supplied with a termination voltage VT1. Termination resistors RT11 and RT12 are respectively connected to the ends of data bus DQBUS and command/address bus CABUS in order to improve the integrity of signals transferred through data bus DQBUS and command/address bus CABUS. Termination resistors a RT11 and RT12 improve the integrity of signals transferred through data bus DQBUS and command/address bus CABUS by preventing signal reflections on the signal lines forming data bus DQBUS and command/address bus CABUS.
Command/address bus CABUS operates at a lower frequency than data bus DQBUS. Accordingly, termination resistor RT12, which prevents reflections of the command/address signal, is located on the motherboard and not on the memory module.
During a read operation performed by data output buffer 121 noise is typically present in reference voltage VREF. This reference voltage is commonly applied to data input buffer 122 and command/address input buffer 123. Thus, an increasing operation speed for semiconductor memory DRAM1 results in an increasing operating speed for data output buffer 121. Where noise is present in the reference voltage VREF, the increasing operating speed of output data buffer 121 produces an undesirable effect in the operation of data input buffer 122 and command/address buffer 123.
Accordingly, separate reference voltages are conventionally applied to data input buffer and command/address buffer 123. A conventional memory system supplying separate reference voltages to a data input buffer and a command/address buffer is shown in FIG. 2.
Referring to FIG. 2, a memory system 200 comprises a memory controller 210, a memory module 220, and termination resistors RT21 and RT22, collectively mounted on a motherboard.
Memory controller 210 transmits a command/address signal to semiconductor memories DRAM1 through DRAMn included in memory module 220 through command/address bus CABUS. The command/address signal controls data being written to or read from semiconductor memories DRAM1 through DRAMn through data bus DQBUS.
Memory module 220 includes semiconductor memories DRAM1 through DRAMn and a command/address buffer 224. Semiconductor memories DRAM1 through DRAMn are connected to data bus DQBUS and command/address bus CABUS, which are system busses connecting memory controller 210. These connections are typically made using a stub, which preferably uses conventional stub series terminated transceiver logic (SSTL).
Command/address buffer 224 buffers the command/address signal transferred through command/address bus CABUS to provide a buffered command/address signal to semiconductor memories DRAM1 through DRAMn.
First semiconductor memory DRAM1 comprises a data output buffer 221, a data input buffer 222 and a command/address input buffer 223. Data output buffer 221 buffers internal output data DOUT and transmits the buffered internal output data to data bus DQBUS. Data output buffer 221 is also called a data output driver. Data input buffer 222 and command/address input buffer 223 implement pseudo-differential operators. Data input buffer 222 amplifies a voltage difference between input data transmitted through data bus DQBUS and a first reference voltage VREF_DQ to generate internal input data DIN which is written to memory cells (not shown) of first semiconductor memory DRAM1.
Command/address input buffer 223 amplifies a voltage difference between the command/address signal transferred through command/address buffer 224 and a second reference voltage VREF_CA to generate an internal command/address signal CAI used for controlling a write or read operation of first semiconductor memory DRAM1.
The levels of first and second reference voltages VREF_DQ and VREF_CA are preferably half a power supply voltage level when all the semiconductor memories DRAM1 through DRAMn are double data rate synchronous RAMs.
Semiconductor memories DRAM2 through DRAMn are identical to semiconductor memory DRAM1 and hence descriptions of the configuration and behavior of semiconductor memory DRAM1 given herein apply to semiconductor memories DRAM2 through DRAMn as well.
Termination resistors RT21 and RT22 are constructed in a parallel termination configuration and provided with a termination voltage VT2. Termination resistors RT21 and RT22 are respectively connected to the ends of data bus DQBUS and command/address bus CABUS in order to improve the integrity of signals transferred through data bus DQBUS and command/address bus CABUS.
As the operation speed of memory system 200 continually increases, the command/address signal transmitted through command/address bus CABUS increases as well. However, memory system 200 cannot appropriately increase the transmission speed of the command/address signal transmitted through command/address bus CABUS because termination resistor RT22, which is connected to the end of the command/address bus CABUS, is mounted on the motherboard.